    1. Multi-Shelf Network Elements
An example of a multi-shelf network element with which the present invention may be used is multi-shelf switch system 100 shown in schematic block form in FIG. 1. Switch system 100 comprises peripheral shelves 110a-n, switching shelves 120a-b, and control complex 130. Peripheral shelves 110a-n provide input/output (I/O) interfaces for connection to data paths 115a-n for which switching services are provided by switch system 100. Switching shelves 120a-b provide the switching services for the system. Control complex 130 provides central management for the switch system. The various shelves of switch system 100 are interconnected by intershelf links 140a-h and 150a-f. An example embodiment of the switch system 100 of FIG. 1 is the Alcatel 7670 Router Switch Platform (RSP) Multi-Shelf system (Alcatel 7670). The Alcatel 7670 is a multiprotocol backbone system designed to switch ATM cells and route IP traffic through the same switching fabric. Depending on its configuration, the Alcatel 7670 provides from 14.4 Gbps up to 450 Gbps of switching capacity.
In one embodiment of switch system 100 of FIG. 1, each of switching shelves 120a-b contains a switching fabric core and up to 32 switch access cards (SAC), each providing 14.4 Gbps of cell throughput to and from the core. Switching shelves 120a-b are configured as a redundant pair and are referred to as switching shelf X and switching shelf Y.
In one embodiment, two types of peripheral shelves 110a-n may be used in switching system 100. The first type, called a high speed peripheral shelf (HSPS), comprises high speed line processing cards (HLPC) each providing 10 Gbps throughput, high speed I/O cards (HIOC), high speed fabric interface cards (HFIC) and two high speed shelf controllers (HSC). The second type, called simply a peripheral shelf (PS), comprises lower speed line processing cards (LPC) each providing 2.5 Gbps throughput, I/O Cards (IOC) and dual or quad port fabric interface cards (DFIC/QFIC). Each of peripheral shelves 110a-n also typically includes a shelf control system which may comprise control complex 130 (in the case of peripheral shelf 110a) or one or preferably two redundant peripheral shelf controllers (PSC).
In one embodiment, switching shelves 120a-b connect to the peripheral shelves 110a-n in the system via fabric interface cards (FIC) to provide cell switching to the line processing cards (also referred to as “line cards”) in the peripheral shelves. Examples of these connections are illustrated in FIG. 2.
FIG. 2 includes two switching shelves 120a (designated “switching shelf X”) and 120b (designated “switching shelf Y”) and three peripheral shelves: two normal speed peripheral shelves 110a (designated “PS1”) and 110b (designated “PS2”) and one high speed peripheral shelf 110c (designated “HSPS3”). In one embodiment, each of the peripheral shelves may comprise up to sixteen (16) line processing cards. In FIG. 2, two line cards 225a-b are shown for peripheral shelf 110a, four line cards 235a-d for peripheral shelf 110b, and four high speed line cards 245a-d for high speed peripheral Shelf 110c. Each pair of line cards in each peripheral shelf communicate with an associated pair of I/O cards, which connect to the data stream for which switching services are being provided. Thus, in the embodiment of FIG. 2, line cards 225a-b communicate with associated I/O cards 220a-b, line cards 235a-b communicate with I/O cards 230a-b, line cards 235c-d communicate with I/O cards 230c-d, high speed line cards 245a-b communicate with I/O cards 240a-b, and high speed line cards 245c-d communicate with I/O cards 240c-d. Each line card is also connected to two redundant fabric interface cards (FIC) which provide high speed connections between each line card and each switching shelf 120a and 120b. One of each pair of FIC's is designated FIC “X” and the other is designated FIC “Y”. Three types of FIC's are shown in FIG. 2. Peripheral shelf 110a contains two dual FIC's (DFIC) 270a and 270b. Peripheral shelf 110b contains two quad FIC's (QFIC) 275a-b, and high speed peripheral shelf 110c contains four high speed FIC's (HFIC) 280a-d. 
In one embodiment, each switching shelf 120a-b comprises a switch core and up to 32 switching access cards (SAC). In the embodiment of FIG. 2, switching shelf X 120a comprises switch core 250a and SAC's 255a-h, and switching shelf Y 120b comprises switch core 250b and SAC's 265a-h. 
In one embodiment, the connections between the various components within a shelf are provided via one or more circuit boards in each shelf, referred to as “midplanes,” to which the respective components are mounted.
In the embodiment of FIG. 2, each “X”-designated FIC on a peripheral shelf is connected to one or more SAC's on switching shelf X 120a, and each “Y”-designated FIC on a peripheral shelf is connected to one or more SAC's on switching shelf Y 120b. A DFIC connects to up to two SAC's, a QFIC to up to four SAC's, and a HFIC to a single SAC. In the embodiment of FIG. 2, the connection between the FIC's on a peripheral shelves 110a-c and the SAC's on switching shelves 120a-b is via high speed intershelf links (HISL) 290a-p, which carry the cell-switched data path traffic. Thus DFIC X 270a of peripheral shelf 110a is connected to SAC's 255a-b on switching shelf X 120a via HISL's 290a-b, and DFIC Y 270b of peripheral shelf 110a is connected to SAC's 265a-b on switching shelf Y 120b via HISL's 290i-j. Similarly, on peripheral shelf 110b, QFIC X 275a is connected to SAC's 255c-f on switching shelf X 120a via HISL's 290c-f, and QFIC Y 275b is connected to SAC's 265c-f on switching shelf Y 120b via HISL's 290k-n. Finally, on high speed peripheral shelf 110c, HFIC's X 280a and 280c are connected via HISL's 290g-h to SAC's 255g-h on switching shelf X 120a, and HFIC's Y 280b and 280d are connected via HISL's 290o-p to SAC's 265g-h on switching shelf Y 120b, respectively.
The switch cores 250a-b, SAC's 255a-h and 265a-h, HISL's 290a-p, and FIC's 270a-b, 275a-b and 280a-d comprise the system's “switching fabric.”
In the switch system of FIGS. 1 and 2, peripheral shelf 110a, designated “Peripheral Shelf 1,” contains control complex 130. In one embodiment, control complex 130 comprises a logical grouping of cards that provide the central management for all features of switch system 100. The local and remote user interfaces to the system are provided by control complex 130 via user terminals 160 and 170. In addition, control complex 130 maintains a database for all cards on the system. One embodiment of control complex 130 is illustrated in FIG. 3.
In the embodiment of FIG. 3, control complex 130 comprises two control cards 300a-b (designated “Control Card A” and “Control Card B”, respectively), two intershelf connection (ICON) cards 310a-b, two control interconnect (CIC) cards 315a-b, two intershelf connection I/O (ICON I/O) cards 320a-b, and two intershelf connection I/O expansion cards (ICON I/O Exp) 330a-b. Control complex 130 also comprises a facility card (FAC) that provides an RS232 management port and two timing ports that can be attached to a timing source for system synchronization. In addition to control complex 130, peripheral shelf 110a also comprises its own set of line processing cards 340 that communicate with control complex 130 via CIC cards 315a-b. 
Control complex 130 communicates with each shelf in the switch system via shelf controllers on the peripheral and switching shelves. In the embodiment of FIG. 3, peripheral shelf 110b comprises a redundant pair of shelf controllers 340a-b, high speed peripheral shelf 110c comprises a redundant pair of high speed shelf controllers 350a-b, and switching shelves 120a and 120b each comprise a switching shelf controller 360a and 360b, respectively.
ICON I/O cards 320a-b and ICON I/O Exp cards 330a-b provide interfaces for connecting control complex 130 to other shelves (such as peripheral I/O and switching shelves) in the switch system via physical connections. In one embodiment, these connections are referred to as Control Services Links (CSL) 370a-h. In the embodiment of FIG. 3, each ICON I/O and ICON I/O Exp card contains eight CSL ports. ICON I/O A 320a and ICON I/O B 320b provide ports for CSL connections to the two switching shelves X and Y 120a-b and to the first six peripheral I/O shelves (designated peripheral shelves 2 to 7), while ICON I/O Exp A 330a and ICON I/O Exp B 330b provide ports for CSL connections to eight additional peripheral I/O shelves (designated peripheral shelves 8 to 15). ICON cards 310, ICON I/O cards 320, ICON I/O Exp cards 330, CSL's 370, and shelf controllers 340, 350 and 360 provide an intershelf connection (ICON) infrastructure that allows the transfer of control traffic between control complex 130 and the controllers and cards in peripheral shelves 110 and switching shelves 120 without using any bandwidth on the main data path. Data path traffic goes through the switching fabric shown in FIG. 2 whereas the control traffic uses the out of band ICON infrastructure (also sometimes referred to as the “control infrastructure”) of FIG. 3 to transfer data. Operation of the control infrastructure is not affected by the switching fabric, and the switching fabric is not affected by the control infrastructure.
In one embodiment, a CSL link is physically embodied in a twelve-conductor cable comprising three separate, internal 4-conductor Cat-5-type cables. Each 4-conductor internal cable provides one of three different types of communications channels: a time division multiplexed (TDM) channel (providing E1-type capabilities), a full duplex (Ethernet) messaging channel, and a simplex differential channel.
The TDM channel (also sometimes referred to as the “E1 channel”) is used by the ICON infrastructure to transport time sensitive transport activity, shelf numbering control and system timing information throughout the system. In one embodiment, the TDM channel operates at a frequency of 8000 Hz, providing 32 time slots with 8-bits per slot at a 125 microsecond refresh rate resulting in a data rate of 2.048 Mbps. In this embodiment, the TDM channel provides a guaranteed point-to-point channel between the ICON cards on peripheral shelf 1 and any shelf connected to one of peripheral shelf 1's CSL ports.
The full duplex messaging channel (also sometimes referred to as the “Ethernet channel”) is used for general communications with any shelf in the system. In one embodiment, the Ethernet channel operates at 100 Mbps. Each Ethernet link to a shelf is shared among all components (cards) within the shelf. As a result, every element in the system is capable of communicating with the control complex via the Ethernet channel.
The Ethernet channel may be used for a large variety of communications, including connection information, software downloading to the individual components, debugging, alarm management, and configuration transfers. Communications between the control complex and the shelf controllers that does not travel over the TDM channel in general travels over the Ethernet channel.
The simplex differential channel (also sometimes referred to as the “RTS channel”) is used to distribute a real time stamp (RTS) from the controller to each of the shelves in the system. The simplex differential channel is used instead of the TDM channel or the Ethernet channel because the RTS is sensitive to time delays that result from the applications running on the TDM and Ethernet channels. The RTS is used to align all elements of the system to the same time stamp for purposes such as debugging and billing. The RTS signal is generated by the control complex and is provided to the ICON cards via a direct circuit board (mid-plane) connection. The ICON cards are responsible for extracting the signal and transmitting it via the differential channel to all shelves in the system.
The use of redundant pairs of control cards and icon cards in peripheral shelf 1 and redundant shelf controllers in other peripheral I/O shelves creates redundant pathways over which control traffic can flow between each control card of the control complex in peripheral shelf 1 and each line card of each peripheral I/O shelf. Examples of redundant pathways between control card 300a and a line card 550 of high speed peripheral shelf 110c are shown in FIGS. 5a-b. For simplicity, only the main relevant components are shown in FIGS. 5a-b. For the same reason, the ICON I/O and ICON I/O Exp cards are not shown separately but are included as part of the respective ICON cards.
A first pathway, shown in FIG. 5a, comprises midplane link 505 between control card A 330a and ICON card A 310c in peripheral shelf 1 110a, CSL link 370c between ICON card A 310c on peripheral shelf 1 110a and shelf controller A 350a on peripheral shelf 2 110c, and midplane link 515 between shelf controller A 350a and line card 550 on peripheral shelf 2 110c. A second pathway, shown in FIG. 5b, comprises midplane link 530 between control card A 330a and ICON card B 310b on peripheral shelf 1 110a, CSL link 370d between ICON card B 310b on peripheral shelf 1 110a and shelf controller B 350b on peripheral shelf 2 110c, and midplane link 525 between shelf controller B 350b and line card 550 on peripheral shelf 2 110c. 
FIG. 4 illustrates the control traffic flow of the pathway of FIG. 5a. In the embodiment of FIG. 4, controller card a 300a comprises a microprocessor 405, a real time stamp source 415, and an Ethernet port 410.
Microprocessor 405 exchanges time sensitive control data and normal control data with line card 420 on peripheral shelf 2 110c. Time sensitive control data travels over a set of “n” direct links 420 to a field programmable gate array (FPGA) 450 on ICON card A 310a. FPGA 450 assembles the data for transmission via TDM, and transmits the time sensitive data via E1 channel 485 of CSL 370c to FPGA 470 of shelf controller A 350a on peripheral shelf 2 110c. FPGA 470 extracts the time sensitive data for line card 420 from the TDM stream, and passes it via direct midplane links 495 to line card 420.
Normal control data, on the other hand, travels from microprocessor 405 to Ethernet port 410 of control card A 300a, and from there via midplane Ethernet link 425 to switch 445 of ICON card A 310a. Switch 445 passes the data via CSL Ethernet channel 490 to switch 465 on shelf controller A 350a of peripheral shelf 2 110c. Switch 465 in turn transmits the data to Ethernet port 482 on line card 420. A microprocessor 466 of shelf controller A 350a on peripheral shelf 2 110c is coupled to FPGA 470 via connection 467, switch 465 via connection 468, and Ethernet port 482 via connection 469, allowing microprocessor 466 access to the time sensitive data and the normal control data and/or allowing microprocessor 466 to exert control over the operations of FPGA 470, switch 465, and/or Ethernet port 482 (or, more generally, line card 420 via Ethernet port 482).
Real time stamp (RTS) source 415 may generate its own time signal, or may receive a time signal from an external source. RTS source 415 communicates its time signal via midplane link 430 to RTS transponder 455 on ICON card A 310a. RTS transponder 455 converts the time stamp into proper form for transmission over the differential channel of CLS 370a and sends it to RTS transponder 475 on shelf controller A 350a of peripheral shelf 2 110c. RTS transponder 475 extracts the RTS signal from CSL 370c's RTS channel and distributes it to line card 420 via midplane link 497.
Even though FIG. 4 only shows the control data pathways between one control card and one ICON card, it will be understood that the same pathways exist between each control card and both of the ICON cards in peripheral shelf 1 110a.    2. APS Automatic Protection System
A common method used to prevent data communications interruptions is known as Automatic Protection Switching (APS) 1+1. In an APS 1+1 system, components are connected via redundant, mirrored links. Each transmitting component sends the identical data over both links, and each receiving component listens to both links. One of the links is the normal “work” link, while the other is the “protection” link. As long as the work link is operating properly, the receiving component processes the data received from that link and discards the data received via the protection link. However, if at any time the work link becomes inoperable or defective, the receiving component immediately begins processing the data received over the “protection” link. Both links must carry identical data so that no data loss occurs when such a switch is made.
APS is useful because it prevents communications failures resulting from a single link failure. However, it does so at the expense of bandwidth: because the same data is sent simultaneously over two separate links, the total bandwidth needed is twice the what is required by the data stream itself, even though the data transferred over the protection link is used only during the infrequent times when there is a failure of the work link, and is otherwise discarded.